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- Path: hydra.zrz.TU-Berlin.DE!rawneiha
- From: rawneiha@hydra.zrz.TU-Berlin.DE (Philipp Boerker)
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: New C2P
- Date: 18 Jan 1996 15:23:35 GMT
- Organization: Technical University of Berlin, Germany
- Message-ID: <4dloln$h49@news.cs.tu-berlin.de>
- References: <4ctiib$2ok@irz305.inf.tu-dresden.de> <38231962@kone.fipnet.fi> <9601111903.AA0041d@dookie.demon.co.uk> <4d5m8o$f38@brachio.zrz.TU-Berlin.DE> <9601141632.AA00423@dookie.demon.co.uk>
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- Jonathan Belson <jon@dookie.demon.co.uk> writes:
-
- >Philipp Boerker (rawneiha@w352zrz.zrz.TU-Berlin.DE) wrote:
-
- >: >For burst mode to make a difference in execution speed, you need static
- >: >column RAM, surely?
- >:
- >: No, you don't. Try your 030 with Instr Burst disabled...
-
- >I tried SysInfo with all combinations of IBurst and DBurst, no difference
- >at all.
-
- >I had a look through one of my university texts : 'During a read miss, the
- >cache may optionally fill the entire cache line from main memory using four
- >longword read operations in a special burst mode. This feature improves
- >the performance of systems with certain types of memory chips that can read
- >from consecutive addresses faster than they can read from "random"
- >addresses' [Wakerly], ie. static column ram.
-
- Hm, maybe that's the reason why the RAM for my Blizzard was so damn
- expensive! (600 DM (400 US$) for 8MB). They said that it was special
- RAM...
- With my accelerator board there is a difference with instr burst
- disabled. The data burst is disabled by default and the performance
- drops if I enable it. Instr burst is enabled by default. I think that
- bus is to busy if you enable both bursts.
-
- Greets,
- Phil.
- ----------------------------
- grond/matrix
- rawneiha@sp.zrz.tu-berlin.de
- ----------------------------
-
-